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methodology_system_desigh_flow_-_language_and_simulation

Methodology & System Desigh Flow - language and simulation



23h

Course objectives



This course provides the fundamental concepts in design methodologies for multi-physical and multidisciplinary systems. It helps students to develop simulation models of digital and mixed-signal hardware systems, mechatronic systems such for biomedical applications. This course addresses the main aspects of the modeling of digital and mixed-signal hardware components and systems using the VHDL-AMS modeling languages. It has as objectives to place the virtual prototyping on these new methodologies, to initiate to disciplinary and multi- abstractions CAD, to establish modeling and simulation models around VHDL-AMS language as an industrial solution.

Course outline


  • Introduction: Challenges of modern system design. Importance of a standard: VHDL-AMS language, VHDL-AMS characteristics (design flow, modeling guidelines).
  • Modeling analog and mixed-signal hardware components and systems: Essential VHDL-AMS language elements and modeling concepts, VHDL-AMS model organization, Behavioral and structural VHDL-AMS * Case Studies: Modeling electrical primitives, mechanical systems, and some examples of industrial uses.
  • Practice Labs: Getting Started with ANSYS-Simplorer environment and introduction to VHDL-AMS language through modeling circuits (pacemaker), and physical modeling multi (integration of mechanical, fluidic, and other components)
  • Project : Design and simulate a complete complex multi-physical system with its environment to meet a set of typical loads of industrial problems, for example a lab on chip, including micro fluidic features, electrical and electronic circuits and biological subsystems. Setting up a high-level behavioral model of the complete system.


Acquired skills


  • Master the modern methods of designing complex systems
  • Creation and use of models of analog and mixed-signal hardware systems at various levels of abstraction.
  • Use of the VHDL-AMS hardware description language.
  • Develop reusable models at various levels of abstraction.


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methodology_system_desigh_flow_-_language_and_simulation.txt · Dernière modification: 2020/10/21 11:27 (modification externe)